Conventionally, imagers have been fabricated with image sensing regions, integrated circuitry, and contacts on the active surface of a silicon wafer. State-of-the-art semiconductor devices, including imagers, typically have dimensions that are as small as possible. Nonetheless, a significant portion of the area, or real estate, on the active surface of an imager is typically occupied by image sensing elements. Accordingly, various other elements, including conductive lines, or traces, must be densely packed into the remaining, typically peripheral, areas of the semiconductor device. When conductive lines, or traces, are densely arranged, cross-talk, capacitance, and other undesirable electrical issues must be resolved. The difficulty in resolving these issues increases the more densely the conductive lines are arranged.
Another factor that sometimes undesirably adds to the area consumed by an imager is the so-called “snowplow” effect that occurs when color filter array (CFA) materials are applied (e.g., by spin coating) over imagers in which the dielectric material (e.g., glass) that overlies the image sensing elements has been thinned relative to the surrounding areas of the imager. Specifically, a peripheral “dead” zone is provided around an array of image sensing elements to accommodate thicker regions of color filter array material so as to avoid the presence of these thicker, or snowplowed, regions over the image sensing elements. The requirement of additional area prevents further decreases in the total area consumed by the imager, or introduces the additional complexities involved in increasing the density of the peripherally confined elements of the imager.
Furthermore, the presence of bond pads on the active surfaces of imagers necessitates that bond wires or other laterally extending intermediate conductive elements be used to electrically connect such imagers to carriers (e.g., circuit boards) and to other electronic components. As bond wires and other laterally extending intermediate conductive elements extend beyond the periphery of an imager to contacts (e.g., terminals) located outside of the periphery of the imager, they and the contacts occupy even more of the real estate upon the carrier, the value of which increases with decreases in acceptable electronic device dimensions.
Several approaches have been taken to address this undesirable occupation of real estate upon carriers for imagers. One approach has been to form through wafer interconnects (TWIs), or conductive vias, through the substrate of an imager. This approach requires that holes be formed through areas of the imager substrate that are not occupied by image sensing elements or integrated circuitry. The requirement of such “dead” area on a substrate, however, contradicts the trend toward maximized density and, thus, prevents optimal minimization of the dimensions of an imager. The other approach has been to form conductive elements that extend around the outer periphery of the imager substrate, which enables optimal circuit density, but effectively adds to the outer dimensions of the finished semiconductor device. Further, any redistribution layers (RDLs), or redistribution circuitry, required by both of these approaches undesirably adds to the overall thickness and cost of the imager.
Accordingly, there are needs for processes in which undesirable electrical effects of imagers may be reduced and contacts may be fabricated on the back sides of imagers while facilitating minimization of the peripheral dimensions of the imagers.